Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory, among others.
Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Flash memory devices are utilized as non-volatile memory for a wide range of electronic applications, including personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones, among others. Program code and system data, such as a basic input/output system (BIOS) which can be used in personal computing systems, are typically stored in flash memory devices.
Flash memories, comprised of a number of strings formed of one or more memory cells, are typically arranged into array architectures, e.g., a matrix. Two common types of flash memory array architectures are the “NAND” and the “NOR” architectures.
In the NOR array architecture, the floating gate memory cells of the memory array are typically arranged in a matrix. The NOR architecture floating gate memory array is accessed using a row decoder to activate a row of floating gate memory cells by selecting a select line coupled to their gates. The data values of the row of selected memory cells are then placed on sense lines, a data value being indicated by the flow of current corresponding to a particular cell being in a programmed state or an erased state.
A NAND architecture also has its array of floating gate memory cells arranged in a matrix such that the control gates of each floating gate memory cell transistor of the array are typically coupled in rows by select lines. However, each memory cell is not independently coupled to a sense line. Instead, the memory cells are electrically coupled together in series, source to drain, between a source line and a sense line, i.e., which is sometimes referred to as bit line, with the drain terminal for each transistor in a string being oriented towards the sense line.
The NAND architecture memory array is also accessed using a row decoder activating a row of memory cells by selecting a select line, e.g., row select, which is sometimes referred to as a word line, coupled to their gates. A high bias voltage is applied to a selected gate's drain line SG(D). The word lines coupled to the gates of unselected memory cells of each string are driven, e.g., at Vpass, to operate the unselected memory cells of each group as pass transistors so that they pass current in a manner that is unrestricted by their stored data values. In this manner, a selected transistor is tested for its ability to conduct current, which flows through each group of series-coupled transistors, restricted only by the selected memory cells of each string, thereby placing the current encoded data values of the row of selected memory cells on the sense lines.
Memory cells in a NAND array architecture can be programmed to a desired state. That is, electric charge can be placed on, or removed from, the floating gate of a memory cell to put the cell into any of a number of stored states. For example, a single level cell (SLC) can represent two states, e.g., a 1 or 0 state, such as to indicate a binary digit (“bit”). Flash memory multi state memory cells, multibit cells, or multi-level cells which are referred to generically hereinafter, both in the specification and the claims, as multi-level cells (MLCs), can be programmed into more than two possible binary states. MLCs allow the manufacture of higher density memories without increasing the number of memory cells since each cell can represent more than one bit. MLCs can have more than one programmed state and one erase state, e.g., a cell capable of representing four bits can have fifteen programmed states and an erased state, e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 1110, 1000, 1010, 0010, 0110, and 0000.
MLC memory stores multiple bits on each cell by using different threshold voltage (Vt) levels for each state that is stored. The difference between adjacent Vt distribution levels may be very small for a MLC memory device as compared to a SLC memory device. The reduced margins between adjacent Vt levels, e.g., representing different program states, can increase the difficulty associated with distinguishing between adjacent program states, which can lead to problems such as reduced data read and/or data retrieval reliability.
In a NAND array architecture, the state of a selected memory cell is determined by sensing a current or voltage variation associated with a particular sense line to which the selected cell is coupled. Since the memory cells are connected in series, the current associated with reading the selected cell passes through several other unselected cells, e.g., cells biased so as to be in a conductive state, coupled to the sense line. Various degradation mechanisms exist which can result in erroneous data reads of non-volatile memory cells. The cell current associated with a string of memory cells, e.g., cells coupled in series between a source line and a sense line, can become degraded over time. Memory cells affected by current degradation mechanisms can become unreliable, e.g., the logical value read from the cells may not necessarily be the logical value written to the cells.
Program/erase cycling is one factor which can affect memory cell performance. Cycle endurance of a memory cell is dependent on the difference in a cell's threshold voltage, VT, between the programmed state and the erased state. As the number of program/erase cycles increases, i.e., cycle endurance, cell current can decrease in some memory cells, resulting in subsequent data read errors. Increasing program/erase cycling is also associated with changes in memory performance, e.g., programming speed decreases and erase speed increases, as well as other changes in operational attributes. Slower programming speed may make the affected cells more susceptible to over-programming. For instance, when a voltage is applied to a particular cell, the conditioning of the cell may cause the cell to be over charged, thereby causing further cell degradation and an incorrect result when read and/or verified.